1. Field of the Invention
The present invention relates to a bus signal control circuit which executes transmission and reception of data, an address, and a control signal between a master device such as a CPU and a slave circuit such as a storage circuit or an input/output circuit through a bus, and a signal processing circuit having the bus signal control circuit.
2. Description of the Related Art
In general, a microcomputer is configured by a CPU, a memory, and a peripheral I/O. At present, microcomputer devices are used in many fields, and an erroneous operation of the microcomputer device caused by an influence of surroundings seriously impacts on society. For this reason, as protection against an erroneous operation of a memory, various methods are provided.
Interface signal lines between a master device such as a CPU and a slave device such as a memory include bus signal lines such as an address bus and a data bus and control signal lines such as a chip enable line and a read/write line.
When a noise or the like is mixed with a signal on the signal lines, a data error or an address error occurs, so that the device may erroneously operate.
In general, as a countermeasure against the erroneous operations, error correction by adding a parity bit or an ECC is performed to data error. Error correction by adding a parity bit is also performed to an address error.
When a master device and a memory are physically separated from each other, for example, when printed circuit boards to be mounted are different from each other and wired by a motherboard, a parity bit is added by the master device, and parity check is performed after information of an address and data is temporarily stored (latched) on the board side on which the memory is mounted. In this case, there is employed a method which inhibits the memory from being accessed on the board side on which the memory is mounted when an address error is detected.
In general, the following method is also performed. That is, when an address error occurs, the same address is read more than once in response to read access, and it is confirmed whether read data are matched with each other to avoid data read from an erroneous address from being read.
Furthermore, in write access, desired address data may not be written. In this case, as a countermeasure against an erroneous operation, it is checked whether the desired address data can be normally written by reading back the written address data. A technique which causes a CPU to output an instruction to write data again if the desired data cannot be read back (read-back error) is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-45214.
A technique which, even though a noise occurs in a bus signal by changing bit states of the bus signal at once, prevents the bus signal from being erroneously recognized by the influence of the noise is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-167530. This technique is a signal control circuit technique which suppresses a noise causing an address error of a DRAM.
According to the technique, signals of two addresses continuously output from the signal control circuit to a dynamic RAM are compared with each other to delay a control signal. For this reason, the address signals can be read in a period except for a period in which a noise occurs. Therefore, it is described that an erroneous address can be prevented from being designated to a dynamic RAM.
However, in the address error handling disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-45214, in both cases, bus abnormality is detected by parity check or read back check. Information of the detected address error is temporarily stored in a memory and then processed by a CPU through an error handling process. Therefore, time corresponding to two steps or more is disadvantageously required for the error handling.
Furthermore, when a master device and a memory are physically separated from each other, address data transmitted from a master device (CPU) side may not be normally received by a slave device (memory) on a reception side. In this case, an address error occurs at an address at which data should be originally written, and the data is written at an erroneous address. In this case, the written data is disadvantageously latently present in the memory of the erroneous address.
According to Patent Document 2, although a bus noise which causes an address error is advantageously controlled, an address error caused by induction of an external noise cannot be controlled.